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march 2010 doc id 11077 rev 2 1/17 17 STA510A 44-volt, 5.5-amp, quad power half bridge features ? multipower bcd technology ? minimum input, output pulse width distortion ? 150-m ? r dson complementary dmos output stage ? cmos compatible logic inputs ? thermal protection ? thermal-warning output ? undervoltage protection ? short-circuit protection description STA510A is a monolithic quad half bridge stage in multipower bcd technology. the device can be used as dual bridge or reconfigured, by connecting pin config to v dd , as a single bridge with double current capability, or as half bridges (binary mode) with half current capability. the device is intended for the output stage of a stereo all-digital high-efficiency (ddx ? ) amplifier which employs a pulse-width modulator driver. the STA510A is capable of delivering an output power of 50 w into 3 ? x 4 channels with thd = 10% at v cc = 37 v in single ended configuration. it can also deliver 100 w + 100 w into 6- ? loads with thd = 10% at v cc = 36 v in btl configuration and 200w into 3 ? with thd = 10% at v cc = 36 v in single paralleled btl configuration. the input pins have a threshold proportional to the voltage on pin vl. powerso36 with exposed pad up (epu) table 1. device summary order code operating temp. range package packaging STA510A 0 to 70 c powerso36 epu tube STA510A13tr 0 to 70 c powerso36 epu tape and reel www.st.com
contents STA510A 2/17 doc id 11077 rev 2 contents 1 audio applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 technical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 logic interface and decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 parallel output / high current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 output filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 applications circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STA510A audio applications circuit doc id 11077 rev 2 3/17 1 audio applications circuit figure 1. audio applications circuit (dual btl) l18 22 h l19 22 h c30 1 f c20 100nf c99 100nf c101 100nf c107 100nf c106 100nf c23 470nf c55 1000 f c21 100nf c58 100nf c58 100nf r57 10k r59 10k r63 20 r98 6 r100 6 c53 100nf c60 100nf c31 220nf c52 330pf r104 20 c109 330pf 15 m3 in1a in1a vl config pwrdn pwrdn fault tristate thwarn thwarn +3.3v in1b vdd vdd vss vss vccsig vccsig gndreg gndclean in2a in1b in2a in2b protection & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m5 m4 17 16 out1a gnd1a out1a vcc1a 14 12 10 11 out1b gnd1b out1b vcc1b 13 l113 22 h l112 22 h c32 220nf +v cc c108 470nf c31 220nf 7 m17 m15 m16 m14 8 9 out2a gnd2a out2a vcc2a 6 4 2 3 out2b gnd2b d00au1148b out2b vcc2b 5 19 31 20 gndsub 1 in2b 32 c110 100nf c111 100nf r103 6 r102 6 8 ? 8 ?
pins description STA510A 4/17 doc id 11077 rev 2 2 pins description figure 2. pin connection (top view) table 2. pin functions pin name description 1 gndsub substrate ground 2, 3 out2b output half bridge 2b 4 vcc2b positive supply 5 gnd2b negative supply 6 gnd2a negative supply 7 vcc2a positive supply 8, 9 out2a output half bridge 2a 10, 11 out1b output half bridge 1b 12 vcc1b positive supply 13 gnd1b negative supply 14 gnd1a negative supply 15 vcc1a positive supply 16, 17 out1a output half bridge 1a gndsub out2b out2b vcc2b gnd1b vcc1a gnd1a out1a out1a gndreg vdd vdd config vl vss vss vccsig vccsig 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 nc gndclean d01au1273 out1b vcc1b out1b pwrdn fault tristate 9 8 7 28 29 30 out2a thwarn 10 27 gnd2b out2a vcc2a in1a in2b in1b 14 12 11 23 25 26 gnd2a in2a 13 24 ep, expos ed pad up
STA510A pins description doc id 11077 rev 2 5/17 18 nc no internal connection 19 gndclean logical ground 20 gndreg ground for regulator v dd 21, 22 vdd 5-v regulator referred to ground 23 vl logic reference voltage 24 config configuration pin: 0: normal operation 1: single btl (mono) mode, join the pins out1a to out1b and out2a to out2b (if in1a is joi ned to in1b and in2a to in2b) 25 pwrdn standby (power down): 0: low power consumption mode 1: normal operation 26 tristate high impedance control: 0: all power amplifiers in high-impedance state 1: normal operation 27 fault (1) fault advisor: 0: fault detected (short circuit or thermal) 1: normal operation 28 thwarn (1) thermal warning advisor: 0: junction temperature = 130 c 1: normal operation 29 in1a input of half bridge 1a 30 in1b input of half bridge 1b 31 in2a input of half bridge 2a 32 in2b input of half bridge 2b 33, 34 vss 5-v regulator referred to +v cc 35, 36 vccsig signal positive supply - ep exposed pad up 1. the pin is open collector. to have a high logic value it needs to be pulled up by a resistor. table 2. pin functions (continued) pin name description
electrical specifications STA510A 6/17 doc id 11077 rev 2 3 electrical specifications 3.1 absolute maximum ratings 3.2 recommended operating conditions (*) performances not guaranteed beyond recommended operating conditions 3.3 thermal data the power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level. the powerso36 package of the STA510A includes an exposed pad or slug on the top of the device to provide a direct thermal path from the die to the heatsink. table 3. absolute maximum ratings symbol parameter min typ max unit v cc dc supply voltage (pins 4,7,12,15) - - 44 v v max maximum voltage on pins 23 to 32 - - 5.5 v t op operating temperature range - - 90 c p tot power dissipation (t case = 70 c) - - 21 w t stg storage temperature -40 - 150 c t j junction operating temperature -40 - 150 c table 4. recommended operating conditions (*) symbol parameter min typ max unit v cc dc supply voltage 10 - 39.0 v v l input logic reference 2.7 3.3 5.0 v t amb ambient temperature 0 - 70 c table 5. thermal data symbol parameter min typ max unit t j-case thermal resistance junction to case (thermal pad) - 1 2.5 c/w t jsd thermal shut-down junction temperature - 150 - c t warn thermal warning temperature - 130 - c t hsd thermal shut-down hysteresis - 25 - c
STA510A electrical specifications doc id 11077 rev 2 7/17 3.4 electrical characteristics the specifications given here were obtained with the conditions v l = 3.3 v, v cc = 36 v, r l =8 ? , f sw = 384 khz and t amb = 25 c unless otherwise specified. see also figure 3 . . table 6. electrical characteristics symbol parameter test conditions min typ max unit r dson power p-channel / n-channel mosfet rdson i d = 1 a - 150 200 m ? i dss power p-channel / n-channel leakage - - - 100 a g n power p-channel rdson matching i d = 1 a 95 - - % g p power n-channel rdson matching i d = 1 a 95 - - % dt_s low current dead time (static) see test circuit in figure 3 -1020ns dt_d high current dead time (dynamic) l = 22 h, c = 470 nf, r l = 8 ?, i d = 3 a, see figure 5 - - 50 ns t d on tu r n - o n d e l ay t i m e resistive load, v cc = 30 v --100ns t d off turn-off delay time resistive load, v cc = 30 v --100ns t r rise time resistive load, see figure 3 - - 25 ns t f fall time - - 25 ns v inh high-level input voltage - - - v l /2 + 300 mv v v inl low-level input voltage - v l /2 - 300 mv --v i inh high-level input current pin voltage = v l -1- a i inl low-level input current pin voltage = 0.3 v - 1 - a i pwrdnh high-level pwrdn pin input current v l = 3.3 v - 35 - a v low low logical-state voltage (pins pwrdn, tristate) v l = 2.7 v - - 0.70 v v l = 3.3 v - - 0.80 v v l = 5.0 v - - 0.85 v v high high logical-state voltage (pins pwrdn, tristate) v l = 2.7 v 1.50 - - v v l = 3.3 v 1.70 - - v v l = 5.0 v 1.85 - - v i ccpwrdn supply current from v cc in power down v pwrdn = 0 v - - 3 ma i fault output current on pins fault and thwarn with fault conditions v pin = 3.3 v - 1 - ma
electrical specifications STA510A 8/17 doc id 11077 rev 2 figure 3. test circuit for low current de ad time for single-ended applications i vcchiz supply current from v cc in 3-state v cc = 30 v, v tristate = 0 v -22-ma i vcc supply current from v cc in operation (both channels switching) v cc = 30 v, input pulse width = 50% duty, switching frequency = 384 khz, no lc filters -70-ma i scp short-circuit current limit - 5.5 6 - a v uvp undervoltage protection threshold - - 7 - v t pw_min output minimum pulse width no load 25 - 40 ns esd esd maximum withstanding voltage range, test condition cdf-aec-q100- 002- ?human body model? +/-1500v v table 6. electrical characteristics (continued) symbol parameter test conditions min typ max unit table 7. logic truth table tristate inxa inxb q1 q2 q3 q4 output mode 0 x x off off off off hi-z 100offoffonondump 1 0 1 off on on off negative 1 1 0 on off off on positive 1 1 1 on on off off not used low current dead time = max(dtr,dtf) outxy vcc (3/4)vcc (1/2)vcc (1/4)vcc t dtf dtr duty cycle = 50% inxy outxy gnd +vcc r 8 ? + - vdc = vcc/2 d03au1458
STA510A electrical specifications doc id 11077 rev 2 9/17 figure 4. block diagram for high current dead time for bridge applications figure 5. test circuit for high current dead time for bridge applications inxa inxb +v cc q1 q3 q2 q4 outxa gnd outxb d00au1134 high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=8 ? q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=4.5a iout=4.5a q4 q1 q3 inb d03au1517 ina dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4.5a in the direction shown in figure l68 22 l67 22 outa
technical information STA510A 10/17 doc id 11077 rev 2 4 technical information the STA510A is a dual channel h-bridge that is able to deliver 100 w per channel (into r l =6 ? with thd = 10% and v cc = 36 v) of audio output power very efficiently. it operates in conjunction with a pulse-width modulator driver such as the sta321 or sta309a. the STA510A converts ternary-, phase-shift- or binary-controlled pwm signals into audio power at the load. it includes a logic interface, integrated bridge drivers, high efficiency mosfet outputs and thermal and short-circuit protection circuitry. in differential mode (ternary, phase-shift or binary differential), two logic level signals per channel are used to control high-speed mosfet switches to connect the speaker load to the input supply or to ground in a bridge configuration, according to the damped ternary modulation operation. in binary mode, both full bridge and half bridge modes are supported. the STA510A includes overcurrent and thermal protection as well as an undervoltage lockout with automatic recovery. a thermal warning status is also provided. figure 6. block diagram of full-bridge ddx ? or binary mode figure 7. block diagram of binary half-bridge mode 4.1 logic interface and decode the STA510A power outputs are controlled using one or two logic-level timing signals. in order to provide a proper logic interface, the vl input must operate at the same voltage as the ddx control logic supply. inl[1,2] inr[1,2] vl pwrdn tristate fault thwarn outpl outnl outpr outnr left h-bridge logic interface and decode protection regulators right h-bridge inl[1,2] inr[1,2] vl pwrdn tristate fault thwarn outpl outnl outpr outnr lefta ?-bridge logic interface and decode protection regulators leftb ?-bridge righta ?-bridge rightb ?-bridge
STA510A technical information doc id 11077 rev 2 11/17 4.2 protection circuitry the STA510A includes protection circuitry for overcurrent and thermal overload conditions. a thermal warning pin (thwarn, pin 28, open drain mosfet) is activated low when the ic temperature exceeds 130 c, just in advance of thermal shutdown. when a fault condition is detected an internal fault signal immediately disables the output power mosfets, placing both h-bridges in a high-impedance state. at the same time the open-drain mosfet of pin fault (pin 27) is switched on. there are two possible modes subsequent to activating a fault. z shutdown mode : with pins fault (with pull-up resistor) and tristate separate, an activated fault disables the device, signalling a low at pin fault output. the device may subsequently be reset to normal operation by toggling pin tristate from high to low to high using an external logic signal. z automatic recovery mode: this is shown in the applications circuits below where pins fault and tristate are connected together to a time-constant circuit (r59 and c58). an activated fault forces a reset on pin tristate causing normal operation to resume following a delay determined by the time constant of the circuit. if the fault condition persists, the circuit op eration repeats until the fault condition is cleared. an increase in the time constant of the circuit produces a longer recovery interval. care must be taken in the overall system design not to exceed the protection thesholds under normal operation. 4.3 power outputs the STA510A power and output pins are duplicated to provide a low-impedance path for the device bridged outputs. all duplicate power, ground and output pins must be connected for proper operation. the pwrdn or tristate pin should be used to set all power mosfets to the high-impedance state during power-up until the logic power supply, v l , has settled. 4.4 parallel output / high current operation when using the ddx mode output, the STA510A outputs can be connected in parallel in order to increase the output cu rrent capability to a load. in this configuration the STA510A can provide up to 200 w into a 3- ? load. this mode of operation is enabled with the pin config (pin 24) connected to pin vdd. the inputs are joined so that in1a = in1b, in2a = in2b and similarly the outputs out1a = out1b, out2a = out2b as shown in figure 9 on page 12 4.5 output filtering a passive 2nd-order filter is used on the STA510A power outputs to reconstruct the analog audio signal. system performance can be significantly affected by the output filter design and choice of passive components. a filter design for 6- or 8- ? loads is shown in the application circuit of figure 8 , and for 4- ? loads in figure 9 and figure 10 .
technical information STA510A 12/17 doc id 11077 rev 2 4.6 applications circuits figure 8. typical stereo full bridge configuration for up to 2x 100 w figure 9. typical single btl configuration for up to 180 w l18 22 h l19 22 h c30 1 f c20 100nf c99 100nf c101 100nf c107 100nf c106 100nf c23 470nf c55 1000 f c21 100nf c58 100nf c58 100nf r57 10k r59 10k r63 20 r98 6 r100 6 c53 100nf c60 100nf c31 220nf c52 330pf r104 20 c109 330pf 15 m3 in1a in1a vl config pwrdn pwrdn fault tristate thwarn thwarn +3.3v in1b vdd vdd vss vss vccsig vccsig gndreg gndclean in2a in1b in2a in2b protection & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m5 m4 17 16 out1a gnd1a out1a vcc1a 14 12 10 11 out1b gnd1b out1b vcc1b 13 l113 22 h l112 22 h c32 220nf +v cc c108 470nf c31 220nf 7 m17 m15 m16 m14 8 9 out2a gnd2a out2a vcc2a 6 4 2 3 out2b gnd2b d00au1148b out2b vcc2b 5 19 31 20 gndsub 1 in2b 32 c110 100nf c111 100nf r103 6 r102 6 8 ? 8 ? 12 h 12 h 100nf film 100nf x7r 100nf x7r 1 f x7r 2200 f 63v 220nf 680nf film 100nf film 100nf 10k 10k 6.2 1/2w 6.2 1/2w 100nf x7r 100nf x7r add. in1a in1a vl config pwrdn npwrdn fault tristate thwarn thwarn +3.3v 100nf 100nf x7r in1b vdd vdd vss vss vccsig vccsig gndreg gndclean in1b in2a 29 23 nc 24 25 27 26 28 30 21 22 33 34 35 36 17 16 18 out1a gnd1b out1a vcc1b 10 13 11 out1b gnd1a out1b 14 +36v 330pf 22 ? 1/2w 4 ? gnd2a 6 2 12 vcc1a 15 vcc2b 4 vcc2a 7 3 out2b gnd2b d04au1545 out2b 5 19 31 20 gndsub 1 in2b 32 8 9 out2a out2a 1 f x7r +36v 220nf
STA510A technical information doc id 11077 rev 2 13/17 figure 10. typical quad half bridge configuration for up to 4x 50 w note: 1 in the above three circuits a pwm modulator as driver is needed. 2 the power estimations were made using the sta321+STA510A demo board. the peak power duration is for t 1 s. l11 22 h l12 22 h c51 1 f c71 100nf c91 1 f 1 f 1 f c81 100nf c31 820 f c21 2200 f c58 100nf c58 100nf r57 10k r59 10k r41 20 r61 5k r62 5k r51 6 c53 100nf c60 100nf c61 100nf 15 m3 in1a in1a vl config pwrdn pwrdn fault tristate thwarn thwarn +3.3v in1b vdd vdd vss vss vccsig vccsig gndreg gndclean in2a in1b in2a in2b protection & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m5 m4 17 16 out1a gnd1a out1a vcc1a 14 12 10 11 out1b gnd1b out1b vcc1b 13 c52 1 f +v cc c62 100nf 7 m17 m15 m16 m14 8 9 out2a gnd2a out2a vcc2a 6 4 2 3 out2b gnd2b d03au1474 out2b vcc2b 5 19 31 20 gndsub 1 in2b 32 c72 100nf c92 1 f c82 100nf r52 6 c41 330pf r42 20 c42 330pf c32 820 f l13 22 h l14 22 h c73 100nf c93 1 f c83 100nf c33 820 f r43 20 r53 6 c74 100nf c94 1 f c84 100nf r54 6 c43 330pf r44 20 c44 330pf c34 820 f r63 5k r64 5k r65 5k r66 5k r67 5k r68 5k 4 ? 4 ? 4 ? 4 ?
package mechanical data STA510A 14/17 doc id 11077 rev 2 5 package mechanical data figure 11. powerso36 epu outlin e drawing package dimension
STA510A package mechanical data doc id 11077 rev 2 15/17 in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. table 8. powerso36 epu package dimension symbol mm inch min typ max min typ max a 3.25 - 3.43 0.128 - 0.135 a2 3.10 - 3.20 0.122 - 0.126 a4 0.80 - 1.00 0.031 - 0.039 a5 - 0.20 - - 0.008 - a1 0.03 - -0.04 0.001 - -0.002 b 0.22 - 0.38 0.009 - 0.015 c 0.23 - 0.32 0.009 - 0.013 d 15.80 - 16.00 0.622 - 0.630 d1 9.40 - 9.80 0.370 - 0.386 d2 - 1.00 - - 0.039 - e 13.90 - 14.50 0.547 - 0.571 e1 10.90 - 11.10 0.429 - 0.437 e2--2.90--0.114 e3 5.80 - 6.20 0.228 - 0.244 e4 2.90 - 3.20 0.114 - 0.126 e - 0.65 - - 0.026 - e3 - 11.05 - - 0.435 - g0-0.080-0.003 h 15.50 - 15.90 0.610 - 0.626 h--1.10--0.043 l 0.80 - 1.10 0.031 - 0.043 m 2.25 - 2.60 0.089 - 0.102 n - - 10 degrees - - 10 degrees r - 0.6 - - 0.024 - s - - 8 degrees - - 8 degrees
revision history STA510A 16/17 doc id 11077 rev 2 6 revision history table 9. document revision history date revision changes october 2004 1 initial release. 11-mar-2010 2 updated description and applications circuits
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